Power IC device

Patent Granted Provided is a power IC device having a low ON resistance at a power MOS transistor section and a high processing speed at a front layer channel MOS transistor section. A method for manufacturing such power IC device is also provided. The plane orientation of the front plane of a chip (2a) is at -8 DEG or more but not more than +8 DEG from the (110) crystal plane of silicon. A P channel type trench power MOS transistor (10) is provided with a trench (3) vertically drilled from the front plane of the chip (2a); a gate region (11) in the trench (3); a reverse channel region (12) at a side wall portion of the trench (3); a source region (14) arranged on the front plane layer of the chip (2a); and a drain region (13) arranged on the rear plane layer of the chip (2a).