Latch circuit

特許 権利維持 [PROBLEMS] To provide a high-speed latch circuit by a differential pair circuit in which a feed through current does not flow. [MEANS FOR SOLVING PROBLEMS] The differential pair circuit of a latch circuit consists of M1 and M2. Inputs DT and DB and clock signals CKT and CKB are complementary signals; and since only any one of M3 and M4 is turned on, a feed through current is not generated in the differential pair circuit. A capacitor C between the M3 and M4 functions as a virtual ground when it is discharged sufficiently, and the M3 operates as a current source even if the M4 is cut off. M5, M7 and M6, M8 constitute two NOT circuits and execute two-state static memory function when the inputs/outputs are connected in a ring form